Computing technologies continue to evolve. Computing designs are incorporating more functionality, higher processing and transmission speeds, smaller sizes, more memory, etc., into smaller more robust architectures. These trends have placed demands on interconnects and data management at the device level.
A conventional interconnect technology is the peripheral component interconnect (PCI) that was initially developed for chip to chip interconnections. Previous improvements in the PCI architecture to provide greater performance have been to increase data widths and increase reference clock frequencies. For example, data widths increased from 32 bits to 64 bits and the reference clock frequency increased from 33.3 megahertz to 66.6 megahertz. Viewed on a system level, these improvements provided an interconnect with higher performance to meet the increasing performance demands brought on by other computing improvements. As architectures evolved and bottlenecks emerged, interconnect technologies have continually had to adapt to best support processing and communication with peripheral components and functionalities.
Interconnect technology has continued to evolve. The example conventional interconnect approach above, PCI, was updated with PCI Express. The changes from PCI to PCI Express represent general improvement trends in the interconnect space. For example, previous interconnect approaches shared parallel bus implementations that became a hindrance with increased reference clock frequencies. Furthermore, higher bandwidth bus segments restricted the number of loads on each segment to essentially a point-to-point interconnection. An advancement over these interconnect technologies utilizes numerous point-to-point interconnections called links, instead of the parallel bus segments. Links may consist of one or more lanes and each lane in turn generally includes a set of differentially driven pairs of bidirectional signal wires. A reduction in bus size from the shared parallel bus implementations was accompanied by incorporating some control and clocking information into the data stream instead of having separate hardware lines between devices. Adoption of this new functionality has been limited, however, and conventionally includes the integrated reference clock into communicated bit streams, addressing information and limited control information.
Interconnect architecture has received even more functionality and improvements. For example, Advanced Switching Interconnect (ASI), sometimes referred to as advanced switching, extends PCI Express functionality to support direct endpoint to endpoint communications channels via logical paths. This allows concurrent logical interconnects that each connect a specific set of resources. Furthermore, ASI can be separated into fabric specific routing and protocol specific Protocol Interfaces, allowing scaling of an ASI fabric as well as support for various protocols.
AS supports unicast (peer-to-peer or one-to-one) and multicast (one-to-many) packet transmissions. Unlike PCI Express, which follows a tree topology, ASI supports any arbitrary fabric topology. An ASI fabric may result in more than one communication path between any pair of communicating devices, known as endpoints. Selection of a path between two such devices may have a significant effect on performance. Choosing such a path may not be a straight forward task and often a simple solution will not result in a best solution. Even with recent architectural changes, conventional interconnect technologies have provided insufficient methods of determining optimal paths between communicating devices.